Generally, when erasing a chip of a large scale integrated flash memory device, the chip divided into a plurality of planes can not be erased at the same time. The reason is that an erasure current and a specification etc. could not be satisfied and therefore an erasure and erasure verification operation are sequentially performed on a plane by plane basis. A conventional method of erasing a flash memory device will be explained hereinafter by reference to FIG. 1.
FIG. 1 is a flow chart for illustrating a conventional method of erasing a flash memory device. The flash memory device comprises four (4) planes.
The flow charge begins from a start signal and then goes to a step 11. Initial value of an internal counter within the chip is set to N=1 where N is the erasure number in accordance with an erase command for the chip in the step 11. After an erasure operation for a first plane P1 is performed at a step 12. In a step 14, it is verified whether the first plane P1 are normally erased. In the above step 14, if the first plane are not normally erased, it goes to a step 15. In the above step 15, it is verified whether N is identical to the final erasure number N1 previously set in the internal counter of the chip. In the above step 15, if N is identical to the final erasure number N1 it goes to a step 26. Then it determines that the plane P1 is a failure and completes the erasure operation. However, in the above step 15, if N is not identical to the final erasure number N1 it goes to a step 13. In the above step 13, it causes the erasure number N to increase and return to the step 12 and then continues to perform the erasure operation.
However, in the above step 14, if the first plane P1 becomes normally an erasure state, it goes to a step 16. Then it performs an erasure operation for the second plane P2 and then goes to a step 17. In the above step 17, it is verified that the second plane P2 is normally erased. In the above step 17, if the second plane P2 is not normally erased, it goes to a step 18. In the above step 18, it is verified whether it is identical to the erasure number N1 previously set in the internal counter of the chip. In the above step 18, if it is identical to the erasure number N1 previously set in the internal counter of the chip, it goes to a step 26. Then it determines that the chip is a failure and then completes the erasure operation. However, in the above step 18, if it is not identical to the erase number N1 previously set in the internal counter of the chip, it goes to a step 27. In the above step 17, it causes the erasure number to increase and return to the step 16 and then continues to perform the erasure operation.
However, in the above step 17, if the second plane P2 becomes normally an erasure state, it goes to a step 19. Then it performs an erasure operation for the third plane P3 and then goes to a step 20. In the above step 20, it is verified that the third plane P3 is normally erased. In the above step 20, if the third plane P3 is not normally erased, it goes to a step 21. In the above step 21, it is verified whether it is identical to the erasure number N1 previously set in the internal counter of the chip. In the above step 21, if it is identical to the erase number N1 previously set in the internal counter N of the chip, it goes to a step 26. Then it determines that the chip is a failure and then completes the erasure operation. However, in the above step 21, if it is not identical to the erase number N1 previously set in the internal counter of the chip, it goes to a step 28. In the above step 28, it causes the erasure number to increase and return to the step 19 and then continues to perform the erase operation.
However, in the above step 20, if the third plane P3 is normally erased, it goes to a step 22. Then an erasure for the fourth plane P4 is performed and then goes to a step 23. In the above step 23, it is verified that the fourth plane P4 is normally erased. In the above step 23, if the fourth plane P4 is not normally erased, it goes to a step 24. In the above step 24, it is verified whether it is identical to the erase number N1 previously set in the internal counter of the chip. In the above step 24, if it is identical to the erasure number N1 previously set in the internal counter of the chip, it goes to a step 26. Then it determines that the chip is a failure and then completes the erasure operation. However, in the above step 24, if it is not identical to the erasure number N1 previously set in the internal counter of the chip, it goes to a step 29. In the above step 29, it causes the erasure number to increase and return to the step 22 and then continues to perform the erasure operation.
However, in the above step 23, if the fourth plane P4 becomes normally an erasure state, it goes to a step 25. Then it determines that all the planes P1 through P4 are normal and completes the erasure operation.
As mentioned above, the conventional method of erasing the chip has a problems of a long erasure time because it sequentially performs an erasure operation and an erasure verification for one plane.